As semiconductors become more complex and transistors become smaller and smaller, power consumption and heat have become limiting factors to the continued pace of chip design and manufacturing. As millions, or even billions, of smaller and faster transistors get packed on to a single chip the size of a thumbnail, power consumption and the amount of heat generated in the processor core becomes a significant technical challenge. In particular, as chip densities increase, off-state current leakage requires more power and generates more heat, and may present a limit to chip size and integration.
One technique for reducing off-state leakage current is to form a well of dopant in the channel between the source and drain regions of the transistor. For example, in an NMOS device, boron may be implanted into the channel using halo, or pocket, implant methods. Similarly, in a PMOS device, phosphorus may be implanted into the channel using such implant methods. During the source drain anneal, the implanted boron (in an NMOS device) or phosphorus (in a PMOS device) diffuses throughout the channel to form a well having a relatively uniform concentration of boron or phosphorus for some depth below the gate. Such a well affects the resistance of the channel between the source and drain such that off-state leakage current (in other words, leakage current between the source and drain when the transistor is off) is reduced.